The present invention relates to a plasma processing method and a plasma processing apparatus (e.g. plasma etching apparatus) having a mechanism for holding a sample or wafer (semiconductor wafer, liquid crystal substrate, etc.) on an electrode (sample stage) by means of the so-called electrostatic chuck (electrostatic attraction), and in particular, to a plasma processing method and a plasma processing apparatus suitable for reducing damage to the inner wall of the processing chamber of the plasma processing apparatus caused by a rise in plasma potential.
In a plasma processing apparatus such as a plasma etching apparatus, a method called “electrostatic chuck” or “electrostatic attraction” is widely used for holding a wafer in the processing chamber. The electrostatic chuck (electrostatic attraction) is a method of holding a wafer on an electrode (sample stage) by electrostatic force which is caused by the potential difference between the wafer and the electrode. The electrostatic chuck has advantages over mechanical holding methods (using a holding member such as a clamp) in that wafer contamination due to contact can be avoided and wafer temperature control is easy (since the whole of the back of the wafer is attracted). Methods for the electrostatic chuck generally include a monopole method (applying electrostatic chuck voltage to one electrode) and a dipole method (using two or more electrodes and generally applying electrostatic chuck voltages of different polarities to the electrodes, respectively).
FIG. 2 is a schematic diagram showing the general composition of a plasma processing apparatus.
An electrostatic chuck power supply 111 is capable of applying DC voltage to an electrode 108 which is embedded in a sample stage 109. The value of the DC voltage will hereinafter be referred to as “ESC voltage (output voltage) of the electrostatic chuck power supply 111”. Average electric potential of the wafer 113 caused by application of output of a biasing high-frequency power supply 110 to the electrode 108 via a capacitor will hereinafter be referred to as “self-bias voltage” (Vdc). The self-bias voltage Vdc is a negative DC voltage. In this case, the potential difference between the electrode 108 and the wafer 113 (i.e. the difference between the ESC voltage and the self-bias voltage Vdc) is the electrostatic chuck voltage (Vchuck). The self-bias voltage Vdc is dependent on the peak-to-peak value (Vpp) of the high-frequency bias power applied to the wafer 113 in the following relationship:α=|Vdc/Vpp|≦0.5where α is a constant which can vary depending on the plasma processing apparatus (0.3-0.45 in a standard plasma processing apparatus).
The peak-to-peak value Vpp can be monitored with a Vpp monitor 112.
FIG. 3 is a graph showing an example of the relationship among the ESC voltage, the self-bias voltage Vdc, the peak-to-peak value Vpp and the electrostatic chuck voltage Vchuck.
The self-bias voltage Vdc appears in the negative region of the graph with an absolute value α×Vpp (positive). As shown in FIG. 3, there exist two ESC voltages that cause the same Vchuck with respect to the value of Vdc. The ESC voltages on the positive side and on the negative side of Vdc will hereinafter be expressed as VESC+ and VESC−, respectively.
In this case, the relationship among the ESC voltages (VESC+, VESC−), the electrostatic chuck voltage Vchuck and the self-bias voltage Vdc can be expressed by the following equations:VESC+=Vdc+Vchuck VESC−=Vdc−Vchuck where Vdc is negative and Vchuck is positive.